The present invention relates generally to electronic circuits, and, more particularly, to a sample-and-hold circuit.
Sample-and-hold circuits are made with a sampling capacitor and switches, which are driven by a single clock phase. The sample-and-hold circuit draws spiky current (i.e., peak voltage) when sampling starts, which leads to high power consumption. The spiky current problem is exacerbated when the sampling capacitor value is high, which is the case for high-resolution linear systems, which imposes a big restriction or a huge power requirement on the circuit driving the sample-and-hold circuit (e.g., amplifier, buffer or filter) because it increases settling error. A simple example is a sample-and-hold circuit inside an ADC (Analog-to-Digital Converter), which is driven by an amplifier such as a Programmable Gain Amplifier (PGA). Different complicated techniques must be used between the sample-and-hold circuit and the PGA to overcome the spiky current problem.
FIG. 1 shows a conventional sample-and-hold circuit 100, which includes a first switch 102, a capacitor 104, and a second switch 106. The first switch 102 receives an input signal from a driving circuit (e.g., a PGA) and is controlled by a clock signal at a first phase Clk. When the first switch 102 is closed, the capacitor 104 receives and is charged by the input signal. The capacitor 104 is discharged when the second switch is closed. The second switch 106 is controlled by the clock signal at a second phase Clke, which typically is a delayed version of the clock signal at the first phase Clk. Thus, the clock signal at the second phase Clke determines a sampling moment of the capacitor 104.
The sample-and-hold circuit 100 operates in sample and hold modes to provide a sampled output signal. That is, when the second switch 106 is closed, the sample-and-hold circuit 100 operates in the sample mode and samples the input signal, and when the second switch 106 is opened, the sample-and-hold circuit 100 operates in the hold mode and holds a voltage level of the sampled input signal in the capacitor 104.
A known solution to limit spiky current is to connect a low-pass filter (LPF) between the driving circuit and the sample-and-hold circuit 100. However, the LPF introduces additional input resistance at the input to the sample-and-hold circuit 100, which degrades ADC linearity. Another solution to limit the spiky current is to introduce a cascode switch between the driving circuit and the sample-and-hold circuit 100. However, the cascode switch, although reducing the peak current, still leads to high power consumption and an increase in circuit area.
Therefore, it would be advantageous to have a sample-and-hold circuit that draws less spiky current and consumes less power and area.